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[755-1] QuickSim Timing Simulations
On last Monday we were discussing how QuickSim (which
is just a logic-level simulator) manages to do timing
simulations for designs that use the scn08hp library.
First, note that these components are mapped to
standard cells, and they are *characterized* timing-wise.
In order to see how this characterizarion looks like,
check (from a nova machine) any of the files with a .ts suffix
in the directory:
/s/mentor/mgc_hep/scn08hp/techfiles/nom
You can see in there that the timing data for QuickSim
come from table lookups. For example, some of the data
in the characterization of the xor-2 gate are:
TABLE TTRANSITION_O_rise [10] = {
# [load(pF)] [slope(nS/V)]
[0.00] = 0.053;
[0.02] = 0.065;
[0.04] = 0.081;
[0.06] = 0.092;
[0.08] = 0.107;
[0.10] = 0.123;
[0.20] = 0.193;
[0.40] = 0.376;
[0.60] = 0.513;
[1.00] = 0.875;
};
TABLE TTRANSITION_O_fall [10] = {
# [load(pF)] [slope(nS/V)]
[0.00] = 0.058;
[0.02] = 0.105;
[0.04] = 0.107;
[0.06] = 0.110;
[0.08] = 0.121;
[0.10] = 0.127;
[0.20] = 0.196;
[0.40] = 0.349;
[0.60] = 0.538;
[1.00] = 0.761;
};
These tables give the slopes of the rise and fall times, respectively,
of the output of the XOR gate for 10 different values
of the output capacitive load. The tool uses linear
interpolation for other values.
There are similar tables for the delay between each of the
inputs and the output.
QuickSim computes the capacitive load at the output of
a gate summing the capacitances of the input pins that
that output drives. For example, you can see in the xor0.ts file
that the input capacitance (in pF) of the two inputs
of an xor-2 gate are:
pin property I1 cap_pin 0.047978;
pin property I0 cap_pin 0.0553989;
All these are of course very different from how Accusim or other
*analog* simulators do timing simulations. Those tools
actually solve the circuit equations for getting the
dynamics of the voltages at each node of the circuit.
Please let me know if you want us to discuss this more tomorrow.
C.
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