[755-1] LVS and Backannotation

[Konstantinos Dovrolis <dovrolis@cs.wisc.edu>]

Folks,

the short demos on Thursday provided us with useful feedback
on some problems with the tools. Please note the following
changes in Tutorial-4:

1. Several people had problems with the LVS checks, although
there was nothing wrong in their layout. I have modified
the tutorial in order to solve this problem. Note that one
more design-viewpoint needs to be created; this one will 
be for IC Trace. Also note that from now on we will be 
using IC Trace(M), instead of IC Trace(D). The former checks 
the layout at the mask-level, while the latter at the device level.

2. Several people noted that the backannotation of the
QuickSim viewpoint with post-layout parasitics did not cause
any timing differences. This is possibly because the parasitics 
are not significant for such relatively small circuits, and additionally, 
QuickSim is not able to do very accurate timing simulations.
I also, however, modified the backannotation procedure, in order
to make mistakes less possible. If you have the time, you can follow
the new procedure, and check if your adder performs any slower 
in the backannotated simulations.

Please make a note of the changes in Tutorial-4. It is important
that you use the modified instructions in the next assignments
and in your project.

C.